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Sebastien FAUCOU

ENSEIGNANT-CHERCHEUR


: Sebastien.Faucouatls2n.fr

Adresses :

Institut universitaire de technologie de Nantes ( IUT Nantes )
La Fleuriaye
2, avenue du Pr Jean Rouxel
BP 539
44475 CARQUEFOU Cedex

Batiment bâtiment 15, étage 1, bureau bureau D113

Centrale Nantes ( CN )
Petit Port
1, rue de la Noë
BP 92101
44321 NANTES Cedex 3

Batiment S, étage 5, bureau 517


Publications référencées sur HAL

Revues internationales avec comité de lecture (ART_INT)

    • [1] D. Solet, J. Béchennec, M. Briday, S. Faucou, S. Pillement. A Study in Specification and Hardware Runtime Verification of Critical Embedded Software. In IEEE Transactions on Dependable and Secure Computing ; éd. Institute of Electrical and Electronics Engineers, 2024.
      https://hal.science/hal-04891957v1
    • [2] A. Bernabeu, M. Briday, S. Faucou, J. Béchennec, O. Roux. Cost-optimal timed trace synthesis for scheduling of intermittent embedded systems. In Discrete Event Dynamic Systems ; éd. Springer Verlag, 2023, vol. 33.
      https://hal.science/hal-03952467v1
    • [3] J. Béchennec, M. Brun, S. Faucou, L. Givel, O. Roux. Testing real-time systems with runtime enforcement. In IEEE Design & Test ; éd. IEEE, 2018.
      https://hal.science/hal-01713193v1
    • [4] S. Faucou, L. Pinho. Guest editorial: real-time networks and systems. In Real-Time Systems ; éd. Springer Verlag, 2018, vol. 54, num. 4.
      https://hal.science/hal-01902125v1
    • [5] K. Tigori, J. Béchennec, S. Faucou, O. Roux. Formal Model-Based Synthesis of Application-Specific Static RTOS. In ACM Transactions on Embedded Computing Systems (TECS) ; éd. ACM, 2017, vol. 16, num. 4.
      https://hal.science/hal-01713063v1
    • [6] S. Cotard, A. Queudet, J. Béchennec, S. Faucou, Y. Trinquet. STM-HRT: A Robust and Wait-Free STM for Hard Real-Time Multicore Embedded Systems. In ACM Transactions on Embedded Computing Systems (TECS) ; éd. ACM, 2015, vol. 14, num. 4.
      https://hal.science/hal-01713171v1

Conférences internationales avec comité de lecture et actes (COMM_INT)

    • [7] H. Reymond, J. Béchennec, M. Briday, S. Faucou, I. Puaut, E. Rohou. SCHEMATIC: Compile-time checkpoint placement and memory allocation for intermittent systems. In IEEE/ACM International Symposium on Code Generation and Optimization (CGO'24), mars 2024, Edinburgh, Royaume-Uni.
      https://hal.science/hal-04345348v2
    • [8] H. Reymond, J. Béchennec, M. Briday, S. Faucou, I. Puaut, E. Rohou. EarlyBird: Energy belongs to those who wake up early. In RTCSA 2024 - 30th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, août 2024, Sokcho, Corée du Sud.
      https://hal.science/hal-04663862v1
    • [9] S. Pillement, M. Mendez Real, J. Pottier, T. Nieddu, B. Le Gal, S. Faucou, J. Béchennec, M. Briday, S. Girbal, J. Le Rhun, O. Gilles, D. Gracia Pérez, A. Sintzoff, J. Coulon. Securing a RISC-V architecture: A dynamic approach. In 2023 Design, Automation and Test in Europe Conference (DATE 2023), avril 2023, Antwerp, Belgique.
      https://hal.science/hal-03906564v1
    • [10] H. Zahaf, I. Olmedo, J. Singh, N. Capodieci, S. Faucou. Contention-Aware GPU Partitioning and Task-to-Partition Allocation for Real-Time Workloads. In RTNS'2021: 29th International Conference on Real-Time Networks and Systems, avril 2021, Nantes, France.
      https://hal.science/hal-03641750v1
    • [11] V. Lostanlen, A. Bernabeu, J. Béchennec, M. Briday, S. Faucou, M. Lagrange. Energy Efficiency is Not Enough: Towards a Batteryless Internet of Sounds. In Proceedings of the International Workshop on the Internet of Sounds (IWIS), septembre 2021, Trento, Italie.
      https://hal.science/hal-03324622v1
    • [12] J. Lagha, J. Béchennec, S. Faucou, O. Roux. Toward an Exact Simulation Interval for Multiprocessor Real-Time Systems Validation. In VALID 2020, The Twelfth International Conference on Advances in System Testing and Validation Lifecycle, octobre 2020, Lisbon, Portugal.
      https://cnrs.hal.science/hal-03006791v1
    • [13] D. Solet, J. Béchennec, M. Briday, S. Faucou, S. Pillement. HW-based Architecture for Runtime Verification of Embedded Software on SOPC systems. In 2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), août 2018, Edinburgh, Royaume-Uni.
      https://hal.science/hal-01804096v1
    • [14] D. Solet, M. Briday, J. Béchennec, S. Faucou, S. Pillement. Hardware Runtime Verification of a RTOS Kernel: Evaluation Using Fault Injection. In 14th European Dependable Computing Conference (EDCC), septembre 2018, Iasi, Roumanie.
      https://hal.science/hal-01874233v1
    • [15] A. Mangean, J. Béchennec, M. Briday, S. Faucou. WCET Analysis by Model Checking for a Processor with Dynamic Branch Prediction. In Verification and Evaluation of Computer and Communication Systems. VECoS 2017, août 2017, Montréal, Canada.In Kamel Barkaoui (éds.), . Springer, 2017.
      https://hal.science/hal-01713094v1
    • [16] D. Solet, J. Béchennec, M. Briday, S. Faucou, S. Pillement. Hardware runtime verification of embedded software in SoPC. In 2016 11th IEEE Symposium on Industrial Embedded Systems (SIES), mai 2016, Cracovie, Pologne.
      https://hal.science/hal-01307973v1
    • [17] L. Givel, J. Béchennec, M. Brun, S. Faucou, O. Roux. Testing real-time embedded software using runtime enforcement. In 11th IEEE International Symposium on Industrial Embedded Systems, IEEE SIES 2016, mai 2016, Krakow, Pologne.
      https://hal.science/hal-01399909v1
    • [18] A. Mangean, J. Béchennec, M. Briday, S. Faucou. BEST: a Binary Executable Slicing Tool. In 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016), juillet 2016, Toulouse, France.In Martin Schoeberl (éds.), . Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik, 2016.
      https://hal.science/hal-01713140v1
    • [19] L. Givel, M. Brun, C. Constant, S. Faucou, O. Roux. Use of runtime enforcement for the test of real-time systems. In 12th IEEE International Conference on Embedded Software and Systems, IEEE ICESS 2015, août 2015, New York, états-Unis.
      https://hal.science/hal-01179648v1
    • [20] K. Tigori, J. Béchennec, S. Faucou, O. Roux. Using formal methods for the development of safe application-specific RTOS for automotive systems. In CARS 2015 - Critical Automotive applications: Robustness & Safety, septembre 2015, Paris, France.In Matthieu Roy (éds.), . , 2015.
      https://hal.science/hal-01193023v1
    • [21] S. Faucou, S. Cotard, J. Béchennec, A. Queudet, Y. Trinquet. A Data Flow Monitoring Service Based on Runtime Verification for AUTOSAR. In 2012 IEEE 14th Int'l Conf. on High Performance Computing and Communication (HPCC) & 2012 IEEE 9th Int'l Conf. on Embedded Software and Systems (ICESS), juin 2012, Liverpool, Royaume-Uni.
      https://hal.science/hal-01713202v1
    • [22] A. Jovanovic, S. Faucou, D. Lime, O. Roux. Real-Time Control with Parametric Timed Reachability Games. In 11th International Workshop on Discrete Event Systems, octobre 2012, Guadalajara, Mexique.
      https://hal.science/hal-00753689v1
    • [23] D. Bertrand, S. Faucou, Y. Trinquet. Temporal isolation for the cohabitation of applications in automotive embedded software. In EDDC - Workshop on Critical Automotive Applications: Robustness and Safety (CARS@EDCC), avril 2010, Valencia, Espagne.
      https://inria.hal.science/inria-00538518v1
    • [24] D. Bertrand, S. Faucou, Y. Trinquet. An analysis of AUTOSAR OS timing protection mechanisms. In 14th Int. Conf. on Emerging Technologies and Factory Automation (ETFA'09), septembre 2009, Majorques, Espagne.
      https://inria.hal.science/inria-00538497v1
    • [25] S. Faucou, P. Hladik, A. Déplanche, Y. Trinquet. Overview of microkernel standards for real-time in-vehicle embedded systems. In 4th Taiwanese-French Conference on Information Technology - TFIT'08, mars 2008, Taipei, Taïwan.
      https://hal.science/hal-00490671v1
    • [26] D. Bertrand, A. Déplanche, S. Faucou, O. Roux. A study of the AADL mode change protocol. In 3rd International UML & AADL Workshop, avril 2008, Belfast, Irlande.
      https://hal.science/hal-00490817v1
    • [27] M. Brun, J. Delatour, S. Faucou, G. Savaton. Retour d’expérience sur l’utilisation déclarative d’un langage de transformation pour la génération de code : de AADL vers OSEK/VDX OS. In IDM07, mars 2007, Toulouse, France.
      https://hal.science/hal-01179695v1
    • [28] P. Hladik, A. Déplanche, S. Faucou, Y. Trinquet. Schedulability analysis of OSEK/VDX applications. In 15th International Conference on Real-Time and Network Systems - RTNS'07, mars 2007, Nancy, France.
      https://hal.science/hal-00490656v1
    • [29] P. Hladik, A. Déplanche, S. Faucou, Y. Trinquet. Adequacy between AUTOSAR OS specification and real-time scheduling theory. In IEEE Second International Symposium on Industrial Embedded Systems - SIES 2007, juillet 2007, Lisbon, Portugal.
      https://hal.science/hal-00490661v1
    • [30] J. Béchennec, M. Briday, S. Faucou, Y. Trinquet. Trampoline - an open source implementation of the osek/vdx rtos specification. In 11th Int. Conf. on Emerging Technologies and Factory Automation (ETFA'06), septembre 2006, Prague, République tchèque.
      https://inria.hal.science/inria-00538492v1
    • [31] H. Habrias, S. Faucou. Linking Paradigms, Semi-formal and Formal Notations. In {Teaching Formal Methods, CoLogNET/FME Symposium, TFM 2004}, 2004, Ghent, Belgium, Belgique.
      https://hal.science/hal-00458172v1
    • [32] H. Habrias, S. Faucou. Some reflections on the teaching of Formal Methods. In Teaching Formal Methods, Workshop, TFM 2003, 2003, Oxford, UK, Royaume-Uni.
      https://hal.science/hal-00458173v1

Conférences nationales avec comité de lecture et actes (COMM_NAT)

    • [33] A. Bernabeu, J. Béchennec, M. Briday, S. Faucou, O. Roux. MORTEM: a new runtime for intermittent computing. In Conférence francophone d'informatique en Parallélisme, Architecture et Système (COMPAS), juillet 2023, Annecy, France.
      https://hal.science/hal-04354069v1
    • [34] A. Bernabeu, J. Béchennec, M. Briday, S. Faucou, O. Roux. Synthèse de traces temporisées à coût optimal pour l'ordonnancement de systèmes embarqués intermittents. In Modélisation des Systèmes Réactifs (MSR'21), novembre 2021, Paris, France.
      https://hal.science/hal-03449539v1

Ouvrages - Chapitres d‘ouvrages et directions d‘ouvrages (OUV)

    • [35] S. Faucou, F. Simonot-Lion, Y. Trinquet. Architecture Description Languages for the Automotive Domain. In Behavioral Modeling for Embedded Systems and Technologies: Applications for Design and Implementation. 07-2009
      https://inria.hal.science/inria-00431438v1
    • [36] A. Déplanche, F. Sébastien. Architecture Description Languages - An Introduction to the SAE AADL. In Modeling and Verification of Real-Time Systems. 2008
      https://hal.science/hal-00490270v1
    • [37] A. Déplanche, F. Sébastien. Description d'architectures pour le temps réel : l'approche AADL. In Systèmes temps réel 1 – Techniques de description et de vérification. 2006
      https://hal.science/hal-00490265v1

Autres publications (AUTRES)

    • [38] H. Reymond, I. Puaut, E. Rohou, S. Faucou, J. Béchennec, M. Briday. Memory Allocation in Intermittent Computing. In COMPAS'2022, juillet 2022, Amiens, France.
      https://hal.science/hal-04385204v1
    • [39] J. Béchennec, A. Bernabeu, M. Briday, S. Faucou. Support d'exécution pour le calcul intermittent. In COMPAS 2021, juillet 2021, Lyon, France.
      https://hal.science/hal-03446983v1
    • [40] D. Solet, S. Pillement, M. Briday, J. Béchennec, S. Faucou. Implémentation matérielle d’un dispositif de vérification en ligne sur un SoPC. In Colloque National GDR SoC-SiP, juin 2016, Nantes, France.
      https://hal.science/hal-01324796v1
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