Home » Fiche   membre
Fiche   membre Retour à l'annuaire  

Mikael BRIDAY

ENSEIGNANT-CHERCHEUR


: Mikael.Bridayatls2n.fr

Page pro : http://pagesperso.ls2n.fr/~briday-m

Adresse :

Centrale Nantes ( CN )
Petit Port
1, rue de la Noë
BP 92101
44321 NANTES Cedex 3

Batiment S, étage 5, bureau 509



Publications référencées sur HAL

Revues internationales avec comité de lecture (ART_INT)

    • [1] A. Bernabeu, M. Briday, S. Faucou, J. Béchennec, O. Roux. Cost-optimal timed trace synthesis for scheduling of intermittent embedded systems. In Discrete Event Dynamic Systems ; éd. Springer Verlag, 2023, vol. 33.
      https://hal.science/hal-03952467
    • [2] R. Parrot, M. Briday, O. Roux. Design and verification of pipelined circuits with Timed Petri Nets. In Discrete Event Dynamic Systems ; éd. Springer Verlag, 2023, vol. 33.
      https://hal.science/hal-03952519
    • [3] R. Kassem, M. Briday, J. Béchennec, G. Savaton, Y. Trinquet. Harmless, a Hardware Architecture Description Language Dedicated to Real-Time Embedded System Simulation. In Journal of Systems Architecture ; éd. Elsevier, 2012, vol. 58, num. 8.
      https://hal.science/hal-00768517
    • [4] M. Briday, J. Béchennec, Y. Trinquet. Retis: a real-time simulation platform. In Journal Européen des Systèmes Automatisés (JESA) ; éd. Lavoisier, 2006, vol. 40, num. 8.
      https://hal.science/hal-00537625

Conférences internationales avec comité de lecture et actes (COMM_INT)

    • [5] H. Reymond, J. Béchennec, M. Briday, S. Faucou, I. Puaut, E. Rohou. SCHEMATIC: Compile-time checkpoint placement and memory allocation for intermittent systems. In IEEE/ACM International Symposium on Code Generation and Optimization (CGO'24), mars 2024, Edinburgh, Royaume-Uni.
      https://hal.science/hal-04345348v2
    • [6] S. Pillement, M. Mendez Real, P. Juliette, N. T., S. Faucou, J. Béchennec, M. Briday, S. Girbal, J. Le Rhun, O. Gilles, D. Gracia Pérez, A. Sintzoff, J. Coulon. Securing a RISC-V architecture: A dynamic approach. In DATE Conference 2023, avril 2023, Antwerp, Belgique.
      https://hal.science/hal-03906564
    • [7] R. Parrot, H. Boucheneb, M. Briday, O. Roux. Expressiveness and analysis of Delayable Timed Petri Net. In 16th IFAC Workshop on Discrete Event Systems WODES 2022, septembre 2022, Prague, République tchèque.
      https://hal.science/hal-03952599
    • [8] R. Parrot, M. Briday, O. Roux. Pipeline Optimization using a Cost Extension of Timed Petri Nets. In 2021 IEEE 28th Symposium on Computer Arithmetic (ARITH), juin 2021, Lyngby, Danemark.
      https://hal.science/hal-03464317
    • [9] R. Parrot, M. Briday, O. Roux. Timed Petri Nets with Reset for Pipelined Synchronous Circuit Design. In 42nd International Conference on Application and Theory of Petri Nets and Concurrency, juin 2021, Paris, France.
      https://hal.science/hal-03266806
    • [10] V. Lostanlen, A. Bernabeu, J. Béchennec, M. Briday, S. Faucou, M. Lagrange. Energy Efficiency is Not Enough: Towards a Batteryless Internet of Sounds. In Proceedings of the International Workshop on the Internet of Sounds (IWIS), septembre 2021, Trento, Italie.
      https://hal.science/hal-03324622
    • [11] D. Solet, J. Béchennec, M. Briday, S. Faucou, S. Pillement. HW-based Architecture for Runtime Verification of Embedded Software on SOPC systems. In 2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), août 2018, Edinburgh, Royaume-Uni.
      https://hal.science/hal-01804096
    • [12] D. Solet, M. Briday, J. Béchennec, S. Faucou, S. Pillement. Hardware Runtime Verification of a RTOS Kernel: Evaluation Using Fault Injection. In 14th European Dependable Computing Conference (EDCC), septembre 2018, Iasi, Roumanie.
      https://hal.science/hal-01874233
    • [13] A. Mangean, J. Béchennec, M. Briday, S. Faucou. WCET Analysis by Model Checking for a Processor with Dynamic Branch Prediction. In Verification and Evaluation of Computer and Communication Systems. VECoS 2017, août 2017, Montréal, Canada.In Kamel Barkaoui (éds.), . Springer, 2017.
      https://hal.science/hal-01713094
    • [14] D. Solet, J. Béchennec, M. Briday, S. Faucou, S. Pillement. Hardware runtime verification of embedded software in SoPC. In 2016 11th IEEE Symposium on Industrial Embedded Systems (SIES), mai 2016, Cracovie, Pologne.
      https://hal.science/hal-01307973
    • [15] A. Mangean, J. Béchennec, M. Briday, S. Faucou. BEST: a Binary Executable Slicing Tool. In 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016), juillet 2016, Toulouse, France.In Martin Schoeberl (éds.), . Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik, 2016.
      https://hal.science/hal-01713140
    • [16] J. Tanguy, J. Béchennec, M. Briday, O. Roux. Reactive Embedded Device Driver Synthesis using Logical Timed Models. In 4th International Conference on Simulation and Modeling Methodologies, Technologies and Applications (SIMULTECH 2014), août 2014, Vienne, Autriche.
      https://hal.science/hal-01142411
    • [17] J. Tanguy, J. Béchennec, M. Briday, S. Dubé, O. Roux. Device driver synthesis for embedded systems. In 18th IEEE International Conference on Emerging Technologies & Factory Automation, septembre 2013, Cagliari, Italie.
      https://hal.science/hal-00942323
    • [18] A. Bullich, M. Briday, J. Béchennec, Y. Trinquet. A compiled Cycle Accurate Simulation for Hardware Architecture. In 5th International Conference on Advances in System Simulation - SIMUL 2013, octobre 2013, VENICE, Italie.
      https://hal.science/hal-00943401
    • [19] G. Savaton, J. Béchennec, M. Briday, R. Kassem. An Architecture Description Language for Embedded Hardware Platforms. In Workshop on OCL and Textual Modelling, TOOLS 2011, 2011, Zürich, Anguilla.
      https://hal.science/hal-01179758
    • [20] J. Béchennec, M. Briday, V. Alibert. Extending HARMLESS Architecture Description Language for Embedded Real-Time Systems Validation. In IEEE International Symposium on Industrial Embedded Systems, juin 2011, Västerås, Suède.
      https://hal.science/hal-00941186
    • [21] R. Kassem, M. Briday, J. Béchennec, Y. Trinquet, G. Savaton. Instruction set simulator generation using Harmless, a new hardware architecture description language. In 2nd Int. Conf. on Simulation Tools and Techniques for Communications, Networks ans Systems (Simutools 2009), mars 2009, Roma, Italie.
      https://inria.hal.science/inria-00538502
    • [22] R. Kassem, M. Briday, J. Béchennec, Y. Trinquet, G. Savaton. Cycle accurate simulator generator using Harmless. In Int. Middle Eastern Multiconference on Simulation and Modelling (MESM'09), septembre 2009, Beirut, Liban.
      https://inria.hal.science/inria-00538508
    • [23] R. Kassem, M. Briday, J. Béchennec, Y. Trinquet, G. Savaton. Simulator Generation Using an Automaton Based Pipeline Model for Timing Analysis.. In International Multiconference on Computer Science and Information Technology (IMCSIT), International Workshop on Real Time Software (RTS'08)., octobre 2008, Wisla, Pologne.In IEEE (éds.), Proceedings of the International Multiconference on Computer Science and Information Technology.. , 2008.
      https://hal.science/hal-00486839
    • [24] J. Béchennec, M. Briday, S. Faucou, Y. Trinquet. Trampoline - an open source implementation of the osek/vdx rtos specification. In 11th Int. Conf. on Emerging Technologies and Factory Automation (ETFA'06), septembre 2006, Prague, République tchèque.
      https://inria.hal.science/inria-00538492

Conférences nationales avec comité de lecture et actes (COMM_NAT)

    • [25] A. Bernabeu, J. Béchennec, M. Briday, S. Faucou, O. Roux. MORTEM: a new runtime for intermittent computing. In Conférence francophone d'informatique en Parallélisme, Architecture et Système (COMPAS), juillet 2023, Annecy, France.
      https://hal.science/hal-04354069
    • [26] A. Bernabeu, J. Béchennec, M. Briday, S. Faucou, O. Roux. Synthèse de traces temporisées à coût optimal pour l'ordonnancement de systèmes embarqués intermittents. In Modélisation des Systèmes Réactifs (MSR'21), novembre 2021, Paris, France.
      https://hal.science/hal-03449539
    • [27] R. Parrot, M. Briday, O. Roux. Réseaux de Petri temporisés pour la conception et vérification de circuits pipelinés. In Modélisation des Systèmes Réactifs (MSR'21), novembre 2021, Paris, France.
      https://hal.science/hal-03587736

Autres publications (AUTRES)

    • [28] H. Reymond, I. Puaut, E. Rohou, S. Faucou, J. Béchennec, M. Briday. Memory Allocation in Intermittent Computing. In COMPAS'2022, juillet 2022, Amiens, France.
      https://hal.science/hal-04385204
    • [29] J. Béchennec, A. Bernabeu, M. Briday, S. Faucou. Support d'exécution pour le calcul intermittent. In COMPAS 2021, juillet 2021, Lyon, France.
      https://hal.science/hal-03446983
    • [30] D. Solet, S. Pillement, M. Briday, J. Béchennec, S. Faucou. Implémentation matérielle d’un dispositif de vérification en ligne sur un SoPC. In Colloque National GDR SoC-SiP, juin 2016, Nantes, France.
      https://hal.science/hal-01324796
Copyright : LS2N 2017 - Mentions Légales - 
 -